Close-up inspection of semiconductor chips.
Temporary bonding and debonding

Help customers with their design needs while increasing efficiency in your own processes with 3M temporary bonding and debonding solutions for semiconductor advanced packaging.


Complete solutions in temporary bonding and debonding

  • To meet new computing and design requirements demanded by IoT, 5G, augmented and virtual reality, and other global technology trends, it’s critical to enable high device density integration in reduced footprint and enhance chip performance. Processes like fan-out wafer-level and fan-out panel-level packaging, 3D through-silicon vias, heterogenous integration and others help meet these demands.

    Sustaining full chip yield requires even more. At 3M, we've developed a solution — the 3M™ Wafer Support System (3M WSS) — that helps customers enable their wafer- and panel-level packaging and their sophisticated fan-out wafer- and panel-level counterparts, by addressing their key thermal and chemical resistance challenges.

Key trends in semiconductor advanced packaging

  • Graphic showing fan-out wafer-level packaging.

    Fan-out wafer-level packaging
    The right adhesive is vital during FOWLP – it must be strong enough to provide support for front-end processed wafers during back-end processing, and debond from the carrier with no substrate damage and minimal residue. Processed wafers are diced and carefully rearranged on a wafer, which is molded to fill gaps. The spaces where gaps have been filled create “fanned out” connection points.

    Fan-out panel-level packaging
    FOPLP takes FOWLP a step further by allowing for packaging and processing dice on a large square panel, which can handle more dice than a wafer, further reducing costs.

    Heterogeneous integration
    Heterogeneous integration takes different components (die, MEMS, sensors, etc.) that have been manufactured in separate processes and combines them into a single overall package. This package delivers better functionality and operational benefits (system-level performance, ownership costs). Again, adhesives are vital – they must be compatible with a variety of housing substrates and remove cleanly without damage.

The 3M WSS — an all-in-one semiconductor wafer-level packaging solution

Suitable for: IGBT, FOWLP, LED, MEMS, 3D TSVs, heterogeneous integration

The 3M WSS — a complete IGBT and wafer-level packaging solution — combines world-class equipment with 3M™ Liquid UV-Curable Adhesive to enable the temporary bonding and debonding processes required for wafer thinning and high-temperature FOWLP and FOPLP processes.

Temporarily bonding to a glass carrier provides a rigid, uniform support surface that minimizes stress on the wafer during the subsequent processing steps, resulting in less warpage, cracking, edge chipping — and higher yields.

  • Individual holding up semiconductor wafer to the light.

    Next steps in 3M WSS innovation

    We’re currently formulating adhesive technology that aims to enable heterogeneous integration by maintaining non-oxide surfaces through ultra-high temperature copper-to-copper bonding processes.

    Reach out to a 3M material expert to learn more about how we’re approaching copper thermocompression and its impact on heterogeneous integration.

    Additional product viability testing for 3M WSS includes:

    • Rheology of spin-coat materials prior to cure
    • UV-cure and time requirements

Temporary bonding and debonding process flow

  • Graphic showing temporary bonding and debonding process flow.

    A. Semiconductor wafer, B. 3M™ Liquid UV-Curable Adhesive, C. 3M™ Light-To-Heat Conversion Release Coating (LTHC Ink), D. Glass carrier, E. 3M™ Wafer De-Taping Tape 3305

  • The 3M WSS brings easy bonding and debonding with high throughput of more than 22 wafers per hour.

    1. Bond the wafer to glass carrier

    • Quick curing without post-thermal curing steps

    2. Backgrinding

    • Good total thickness variation (TTV) after backgrinding (typically 2um TTV for 300mm wafer)

    3. Backside processing

    • Good heat resistance (up to 180 °C/266 °F , for 1 hour)
    • Good chemical resistance to a broad range of process chemistries, low outgas

    4. Dicing tape application

    5. Laser debonding

    6. Glass carrier lift-off

    • Without stress

    7. Peel off UV adhesive layer

    • Easy, clean removal

Featured products

Fewer defects. More profitability.

For more than 100 years, 3M has made product testing an essential part of delivering high-quality solutions. Adhesives used for the 3M WSS undergo strict adhesion, thermal and chemical resistance testing, so they can withstand new process, time, temperature and substrate requirements needed for fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP).

  • Graphic showing a cross-section of semiconductor adhesion process.

    We analyze material properties including:

    • Adhesion to silicon and other treated surfaces after application and thermal exposure
    • Chemical resistance to specific processes (electroplating, etc.) and weight loss/gain following wafer immersion for set periods of time and temperatures (polishing, etc.)
    • Weight loss after thermal processing (dielectric cure, plasma, sputtering, etc.)
    • Residue
    • Physical properties of adhesive (modulus, Tg, tensile properties/elongation, etc.)

    For specific thermal, time and chemistry requirements, 3M technical experts can work with you and your team to identify a potential solution with direct support from global product development labs and manufacturing sites.

Connect with a 3M expert about the 3M WSS

We’ve got a team of experts with decades of problem-solving experience and training in relevant technologies ready to help you tackle your toughest material challenges.

Contact Us