Header graphic displaying semiconductor dies on a wafer being inspected.
Process protection

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3M solutions for semiconductor advanced packaging process protection

  • With emerging technologies including 5G, autonomous driving, IoT and others creating an even greater demand for high performance computing and device connectivity, a driving force has been created that will shape the next several generations of technology and design innovation.   Semiconductor chips must be smaller, thinner, faster and more functional.  Advanced IC packaging is key to helping enable the performance needs but requires more and newer processes than ever before – and involves more chemicals, more films, and more extreme processing conditions. Learn how 3M can help.


Protecting more than just processes

  • 3M delivers process protection solutions that help improve your total cost of ownership, including chip yield and process time. Backed by decades of experience in adhesives and electronics, our experts can help you maximize processes for today and for what’s next – heterogenous and integrated die packaging, multiple die stacks and chiplet processing to name a few. Our solutions also help enable the integration of components like sensors, diodes, advanced substrates and more.

  • Key trends in semiconductor advanced packaging

    Embedded die in substrate
    A popular option for reducing form factor is embedded die in substrate. This innovative approach implants the IC within a laminate substrate, which can then be situated next to other components (other dice, MEMs, etc.) using copper-plated vias resulting in an integrated, multi-functional package.

    Heat resistant and chemical resistant process protection solutions from 3M can enable the thermal and chemical processing steps of embedded die in substrate technology.


Discover 3M process protection solutions

Our solutions are designed for a broad range of processes including FOPoP, D2W hybrid bonding, RDL-last processes and others.

Bump protection

Bump protection solutions from 3M

Let us help you achieve new levels of semiconductor chip assembly

Compatible with a variety of surfaces, 3M bump protection tapes are used for processes like FOPoP and RDL-last as well as applications incorporating embedded die substrates, D2W hybrid bonding and others. Backed by more than a century of experience in adhesives and electronics, they allow for higher thermal budgets, clean removal and added chemical resistance during processing.

  • Graphic of semiconductor chip highlighting wafer bumps

    Still to come

    High-temperature bump protection tapes withstand a wide range of heat processes as well as DRAM stacking and reflow in FOPoP, helping prevent bump deformation. A multi-layer version combines material properties from current backgrinding and high-temperature tapes, eliminating the need for two protection tapes for backgrinding, sputtering, etc.

    Also, tapes featuring a first-known rubber-based adhesive can provide greater thicknesses, reduced die shift and clean removal on small embedded components.


Process flow for fan out package on package

  • Step-by-step graphic of the fan out package on package process flow.

    A. Tape, B. Metal frame, C. Die, D. RDL, E. Packaged die

  • 1. Tape lamination on metal frame
     

    • Easy lamination

    2. Attach wafer/dies on tape
     

    • High adhesion at room temperature

    3. Up to multiple cycles of die bonding (120 °C/248 °F - 180°C/356 °F) reflow (250 °C/482 °F - 260 °C/500 °F) and molding process
     

    • Good bump protection during high temperature processes without causing bump damage

    4. Post process – tape removal and inspection
     

    • Low adhesion after heat processes for easy debond
    • Clean removal after debonding

Process flow for embedded die in package

  • 1. Tape lamination on FR4 epoxy panel and Copper surface (PCB)

    2. Die bonding on the tape surface

    3. Apply prepreg and die embedding
     

    • Good die shift performance

    4. Prepreg thermal curing
     

    • Good heat resistance (up to 200 °C/392 °F, for 2 hour)
    • Strong adhesion during high temperature process

    5. Tape removal
     

    • Easy removal
    • No residue on die / bump after removal
  • Step-by-step graphic of the embedded die in package process flow.

    A. FR4 substrate, B. FR4 panel open, C. Copper, D. Tape, E. Prepreg


Process flow for BGBM with bumped wafer

  • Step-by-step graphic of the BGBM with bumped wafer process flow.

    A. Solder bump, B. Bump protection tape, C. EMI shielding

  • This product is still under development. Technical benefits within the process flow are for reference only.

    1. Lamination of bump protection tape
     

    • Good bump absorption(up to 250um bump height), high initial adhesion

    2. Backgrinding (BG) (Optional)
     

    • Good total thickness variation (TTV) and warpage after BG process (down to 300um Si thickness)

    3. Backside processing with heat and chemicals (sputtering for EMI shielding, Die Bonding, etc)
     

    • Good heat resistance (150 °C/302 °F - 200 °C/392 °F multiple hours), good chemical resistance, low outgas

    4. Die saw and die pick up from the tape
     

    • Easy removal with superior clean bump surface

Sensor protection

Explore sensors in new surroundings

Expanded possibilities in semiconductor design

  • Heat resistant polyimide tapes for semiconductor IC packaging process protection.

    3M™ Heat Resistive Polyimide Tapes are excellent for helping protect sensors – valuable components which must endure extensive high-temperature and chemical processing steps in semiconductor assemblies. Not only that, they help you expand your design possibilities. These tapes are compatible with sensor housing materials such as diffusers, epoxy, poly amide, LCP and others, and bond without delamination or siloxane outgassing. They remove easily without residue, staining or static which can damage the substrate. Our semiconductor tapes for sensors meet clean room manufacturing standards.


Process flow for sensor protection

  • Step-by-step graphic of the sensor protection process flow.

    A. 3M™ Heat Resistive Polyimide Tape, B. Cover glass, C. Sensor chip, D. Housing

  • 1. Taping on sensor packages

    2. Reflow process for one or more cycles
     

    • Good heat resistance for multiple reflow cycles at 260 °C/500 °F without delamination
    • No siloxane outgas

    3. Dl water/solvents cleaning process

    4. Removal of tape and inspection of residue
     

    • Clean removal
    • Antistatic performance

QFN

High-performance lamination and masking solutions

Smoother, faster leadframe production

A selection of 3M leadframe tapes help speed production and reduce waste during die bonding, Au/Cu wire bonding and molding. Many of our heat-resistant QFN leadframe masking tape solutions are engineered to withstand the higher soldering temperatures required as the industry moves toward Cu wire bonding. Our laminating leadframe tapes deliver excellent ball shear performance, limiting die tilting and increasing throughput.


Process flow for leadframe tapes

  • Step-by-step graphic of the leadframe tape process flow.

    A. Leadframe, B. Die, C. Tape, D. Wire, E. Molding

  • 1. Tape lamination on leadframe
     

    • Easy lamination

    2. Die bonding
     

    • Good heat resistance (up to 210°C/410 °F, for 30 minutes)

    3. Au/Cu wire bonding
     

    • Good heat resistance (up to 230°C/446 °F, for 30 minutes)

    4. Plasma cleaning
     

    • Good plasma resistance (up to 30 minutes)

    5. Molding
     

    • Good heat resistance (up to 190°C/374 °F, for 5 minutes)
    • Good ball shear performance – less die tilt

    6. Dicing, tape removal and final product
     

    • Easy peel off
    • Clean removal on leadframe and molding component
    • Good plasma resistance for plasma cleaning


Whitepaper: Heat resistant bump protection tape with easy debonding

  • Icon of a whitepaper and desktop.

    To understand the performance of tapes in protection of solder bumps against the critical challenges of advanced packaging, 3M conducted several adhesive formulation DOEs featuring simulated advanced packaging processes requiring higher temperatures. A high temperature 180°C/410 °F / 1 hr + 260°C/500 °F / 10 min bake step was performed to simulate various processes such as sputtering, molding, plasma clean and die attach and the final solder reflow step. We evaluated formulations at targeted levels of adhesive crosslinking, finding that crosslink density correlates strongly with the relative amount of bump damage or distortion. The adhesive becomes stronger as the crosslink density is increased, providing better support to bumps when solder balls soften and melt when at or near the reflow temperature.


Product comparison table for heat resistance process tapes

• = Good •• = Better ••• = Best

*Peeling force on Cu
**Peeling force on bumped wafer


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