Highly repeatable performance and efficiency in semiconductor manufacturing with 3M™ Trizact™ CMP Pads.
With trends like IoT, smart cities, connected transportation, mobile and edge computing driving our world, semiconductors that deliver more memory and speed are in demand. The pressure is on to deliver performance and cost-effective consistency to the Chemical Mechanical Planarization (CMP) process of semiconductor manufacturing. Demand to continually increase yield leaves no room for variation in a fab's production that risks waste or device reliability. 3M is redefining CMP products with our 3M™ Trizact™ CMP Pads to ensure consistent CMP process performance.
Our 3M™ Trizact™ CMP Pads blend 3M’s know-how in molding, surface modification and microreplication, delivering an innovative pad for Chemical Mechanical Polishing for advanced node semiconductor manufacturing.
Designed to deliver the CMP performance you need, 3M™ Trizact™ CMP Pads are engineered using our proprietary microreplication process. The result is a pad that is consistent and well characterized helping to ensure that tomorrow’s pad is the same as today’s.
Consistent and repeatable CMP performance leads to increased yield. 3M™ Trizact™ CMP Pads help increase planarization efficiency, reduce defects, and improve productivity and output.
Our proprietary approach to microreplication helps to deliver a longer pad life and eliminates the need for a diamond pad conditioner.
At the core of the 3M™ Trizact™ CMP Pad is one of 3M’s core technology platforms — microreplication. This technology allows us to deliver excellent uniformity to surfaces with precisely sculpted microscopic features. While this technology was originally born to deliver light management properties to overhead projectors, it has since been extended to tens of thousands of 3M products.
Technical paper published by The Electrochemical Society (ECS), August 2016
Within-die non-uniformity (WIDNU) determined by gate height range among 3 different devices, and by the range in dielectric thickness on top of gate (i.e., TS dielectric) between 3 different devices. One center die, one middle die, and one edge die from wafers polished with POR and MR pads are submitted for cross-sectional TEM analysis, from which gate height and dielectric thickness measurements are taken.
Authors: Wei-Tsu Tseng, Kaushik Mohan, Ricky Hull, James Hagan, Connie Truong, Duy K. Lehuu, and David Muradian
A microreplicated (MR) pad with regulated long-range order surface pore-asperity patterns is used for the buff polish step in a 3-platen W-CMP process for 14 nm replacement metal gate (RMG) and trench salicide (TS) planarization. This new pad requires no diamond tip conditioner and can last up to 2000 wafer passes with highly repeatable removal rates, while maintaining low and consistent defects and within-wafer uniformity. The MR pad also provides unique benefits of mitigating within-die non-uniformity as demonstrated by gate electrical conductance tests and confirmed by physical thickness measurement through cross-sectional TEM.
In addition, topography-driven defects are reduced significantly. The mechanisms responsible for the unique performance of MR pads will be elucidated and the significance of this new CMP pad technology will be discussed.
Technical paper published by Institute of Electrical and Electronics Engineers (IEEE), May 2017
Authors: Wei-Tsu Tseng, Changhong Wu, James Hagan, Yanni Wang, Hong Lin, Ja-Hyung Han, Dinesh Koli
With advanced nodes selecting cobalt for more and more layers, it is becoming a greater challenge to maintain within-die non-uniformity for control or gate height and trench height. Read more about the 3M™ Trizact™ CMP Pad for Cobalt buff CMP defectivity and topography performance presented by Global Foundries at the 2017 IEEE International Interconnect Technology Conference (IITC).
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